We have delved into compiler optimisations and their impact on performance, specifically focusing on the GCC toolchain and its code generation for RISC-V. This work is conducted as a collaboration between BayLibre and Rivos and sponsored as part of the RISE Project. It is centered around the SPEC CPU 2017 benchmark suite, aiming to identify and analyse performance discrepancies between AArch64 and RISC-V implementations, with a view to bridging this gap.
Compiler and architecture interactions
The study examined several aspects, including compiler optimisations, Instruction Set Architecture (ISA) features, and library interactions. The goal was to understand how these elements contribute to overall performance and pinpoint areas of improvement so as to make the quality of the code generated by GCC for RISC-V closer to AArch64.
Areas of investigation
Several areas were identified with potential opportunities for performance improvement. These included:
- Vectorisation and parallelism: The study analysed how the compiler leveraged vector instructions and how architectural parameters influenced the degree of parallelism achieved. Differences in vector length multipliers and their impact on instruction counts were observed.
- Addressing modes: Variations in addressing modes between architectures were examined, particularly their effects on memory access patterns and instruction efficiency. The absence of scaled addressing modes in the RISC-V ISA was noted as a significant factor.
- Library optimisations: The study also considered how library implementations, such as `memset` and math functions, affected overall performance. Differences in optimised implementations and their impact on execution time were analysed. For instance, we found the lack of vectorised routines in RISC-V’s libc had a notable effect.
- Compiler code generation: The compiler’s ability to generate efficient code for specific instruction patterns was investigated. Instances where the compiler could produce more optimal instructions, such as vector-scalar operations, were identified.
Implications for performance
The findings highlight the complex interplay between compiler optimisations, architectural features and library support. The study suggests that performance can be significantly influenced by:
- Compiler strategies: How the compiler chooses to vectorise code, utilise addressing modes, and handle library calls.
- ISA characteristics: The specific instructions and addressing modes available in the target architecture.
- Library implementations: The availability of optimised library functions tailored to the architecture.
Ongoing work and future presentation
The study represents an ongoing effort to improve compiler performance and understand the nuances of different architectures. Further investigations are planned to explore additional areas for improvement. We will shortly be submitting patches addressing some of the weaknesses identified in GCC code generation for RISC-V.
A more in-depth presentation of this analysis and its findings will be shared at the upcoming RISC-V Summit Europe 2025 (https://riscv-europe.org/summit/2025/).