Paris was paradise for Linux kernel developers and embedded software engineers last week with Embedded Recipes and Kernel Recipes returning for the first time since 2019. The BayLibre team enjoyed reconnecting with our fellow open source collaborators while also welcoming newcomers into the Linux development community.
Three engineers from BayLibre made presentations and then fielded questions from those in the audience who managed to catch the famous “flying microphone” box:
Have no fear, this isn’t a military tale! Rather an overview of the mechanism used to implement system calls in the Zephyr operating system. This presentation will quickly introduce the Zephyr system call model, then focus on how it is implemented. We’ll discuss the unsuspected minefield of portable argument passing across different architectures, then the pitfalls of compiler optimization (or lack thereof) and look at various attempt at making it work for everyone all the time. While Zephyr material is used, this presentation ultimately is more about how to (ab)use the C language in such a low-level context so no prior Zephyr knowledge is necessary.
Currently, to support AI/ML hardware accelerators, SoC vendors develop their own drivers, reimplementing a lot of features common to many hardware accelerators.
libAPU aims to provide a stack generic enough to support many AI/ML hardware accelerators. libAPU relies on DRM to manage memory and schedule requests. It uses RPMsg to communicate with the hardware accelerator. It uses remoteproc to power up the hardware accelerator and load the firmware.
Alexandre Bailon will present the libAPU, talks about what has been already implemented, what remains to do and the upcoming challenges.
It is an exciting time for Linux on RISC-V, the open instruction set (ISA) that is quickly gaining critical mass. I will introduce the pieces needed to boot Linux on RISC-V including the Privileged Architecture, OpenSBI and U-Boot, and how that fits into the upcoming RISC-V Platform Specification. I will break down support for existing hardware and current upstreaming efforts. I will also discuss how the arch/riscv maintenance guidelines try to avoid unnecessary churn as the landscape of RISC-V extensions continues to evolve.
The presentation is on Google Slides.