The BayLibre team is very excited that one of our favorites weeks of the year is about to begin – for the first time in 3 years!
Zephyr system call argument marshaling war story – Nicolas Pitre
Have no fear, this isn’t a military tale! Rather an overview of the mechanism used to implement system calls in the Zephyr operating system. This presentation will quickly introduce the Zephyr system call model, then focus on how it is implemented. We’ll discuss the unsuspected minefield of portable argument passing across different architectures, then the pitfalls of compiler optimization (or lack thereof) and look at various attempt at making it work for everyone all the time. While Zephyr material is used, this presentation ultimately is more about how to (ab)use the C language in such a low-level context so no prior Zephyr knowledge is necessary.
A path to upstream AI/ML accelerators – Alexandre Bailon
Currently, to support AI/ML hardware accelerators, SoC vendors develop their own drivers, reimplementing a lot of features common to many hardware accelerators.
libAPU aims to provide a stack generic enough to support many AI/ML hardware accelerators. libAPU relies on DRM to manage memory and schedule requests. It uses RPMsg to communicate with the hardware accelerator. It uses remoteproc to power up the hardware accelerator and load the firmware.
Alexandre Bailon will present the libAPU, talks about what has been already implemented, what remains to do and the upcoming challenges.
After Embedded Recipes concludes on Tuesday, the venue then transitions to Kernel Recipes. The 3-day event kicks off Wednesday, June 1st, and it will also be live streamed. Drew Fustini from BayLibre will speak on Friday morning at 10h:
It is an exciting time for Linux on RISC-V, the open instruction set (ISA) that is quickly gaining critical mass. I will introduce the pieces needed to boot Linux on RISC-V including the Privileged Architecture, OpenSBI and U-Boot, and how that fits into the upcoming RISC-V Platform Specification. I will break down support for existing hardware and current upstreaming efforts. I will also discuss how the arch/riscv maintenance guidelines try to avoid unnecessary churn as the landscape of RISC-V extensions continues to evolve.